数字集成电路设计：从VLSI体系结构到CMOS制造（英文版） [Digital Integrated Circuit Design From VLSI Architectures to CMOS Fabrication] pdf epub mobi txt 电子书 下载 2025

简体网页||繁体网页

☆☆☆☆☆

Hubert Kaeslin 著

图书标签:

• VLSI
• 集成电路设计
• CMOS
• 数字电路
• 芯片设计
• 半导体
• 电子工程
• 微电子学
• 电路分析
• 制造工艺

出版社： 人民邮电出版社

ISBN：9787115223586

版次：1

商品编码：10064342

包装：平装

丛书名： 图灵原版电子与电气工程系列

外文名称：Digital Integrated Circuit Design From VLSI Architectures to CMOS Fabrication

开本：16开

出版时间：2010-

编辑推荐

　　今天，集成电路设计技术高速发展，在各个领域得到广泛应用，已经成为一种横跨多学科的技术。《数字集成电路设计：从VLSI体系结构到CMOS制造(英文版)》从架构与算法讲起，介绍了功能验证、VHDL建模、同步电路设计、异步数据获取、能耗与散热、信号完整性、物理设计、设计验证等必备技术，还讲解了VLSI经济与项目管理，并简单阐释了CMOS技术的基础知识，全面覆盖了数字集成电路的整个设计开发过程。
　　作为一本教科书，《数字集成电路设计：从VLSI体系结构到CMOS制造(英文版)》向工程专业学生展示了数字VLSl设计之美。揭示了各种技术难点，使他们避免重复前人的错误；作为一本技术参考书，《数字集成电路设计：从VLSI体系结构到CMOS制造(英文版)》内容全面，丰富的表格、清单、电路图和个案研究能够帮助正在开发硬件电路的在职工程师更好地完成自己的设计。
　　《数字集成电路设计：从VLSI体系结构到CMOS制造(英文版)》特点
　　·涵盖了数字VLSI设计的大部分问题
　　·从算法设计到晶圆生产，以自顶向下方式一一讲述
　　·重点阐释了流行的CMOS技术和静态电路
　　·全面覆盖数字VLSI设计者需要知道的半导体物理知识
　　·图文并茂，深度体现课堂教学和实际设计项目验证的思想

内容简介

　　《数字集成电路设计：从VLSI体系结构到CMOS制造(英文版)》从架构与算法讲起，介绍了功能验证、VHDL建模、同步电路设计、异步数据获取、能耗与散热、信号完整性、物理设计、设计验证等必备技术，还讲解了VLSI经济运作与项目管理，并简单阐释了CMOS技术的基础知识，全面覆盖了数字集成电路的整个设计开发过程。
　　《数字集成电路设计：从VLSI体系结构到CMOS制造(英文版)》既可作为高等院校微电子、电子技术等相关专业高年级师生和研究生的参考教材，也可供半导体行业工程师参考。

作者简介

　　Hubert Kaeslin，1985年于瑞士苏黎世联邦理工学院获得博士学位，现为该校微电子设计中心的负责人，具有20多年教授VLSI的丰富经验。

内页插图

目录

Chapter 1　Introduction to Microelectronics　1
1.1　Economic impact　1
1.2　Concepts and terminology　4
1.2.1　The Guinness book of records point of view　4
1.2.2　The marketing point of view　5
1.2.3　The fabrication point of view　6
1.2.4　The design engineers point of view　10
1.2.5　The business point of view　17
1.3　Design flow in digital VLSI　18
1.3.1　The Y-chart， a map of digital electronic systems　18
1.3.2　Major stages in VLSI design　19
1.3.3　Cell libraries　28
1.3.4　Electronic design automation software　29
1.4　Field-programmable logic　30
1.4.1　Configuration technologies　30
1.4.2　Organization of hardware resources　32
1.4.3　Commercial products　35
1.5　Problems　37
1.6　Appendix I： A brief glossary of logic families　38
1.7　Appendix II： An illustrated glossary of circuit-related terms　40

Chapter 2　From Algorithms to Architectures　44
2.1　The goals of architecture design　44
2.1.1　Agenda　45
2.2　The architectural antipodes　45
2.2.1　What makes an algorithm suitable for a dedicated VLSI architecture?　50
2.2.2　There is plenty of land between the architectural antipodes　53
2.2.3　Assemblies of general-purpose and dedicated processing units　54
2.2.4　Coprocessors　55
2.2.5　Application-specific instruction set processors　55
2.2.6　Configurable computing　58
2.2.7　Extendable instruction set processors　59
2.2.8　Digest　60
2.3 A　transform approach to VLSI architecture design　61
2.3.1　There is room for remodelling in the algorithmic domain　 62
2.3.2　...and there is room in the architectural domain　64
2.3.3　Systems engineers and VLSI designers must collaborate　64
2.3.4　A graph-based formalism for describing processing algorithms　65
2.3.5　The isomorphic architecture　66
2.3.6　Relative merits of architectural alternatives　67
2.3.7　Computation cycle versus clock period　69
2.4　Equivalence transforms for combinational computations　70
2.4.1　Common assumptions　71
2.4.2　Iterative decomposition　72
2.4.3　Pipelining　75
2.4.4　Replication　79
2.4.5　Time sharing　81
2.4.6　Associativity transform　86
2.4.7　Other algebraic transforms　87
2.4.8　Digest　87
2.5　Options for temporary storage of data　89
2.5.1　Data access patterns　89
2.5.2　Available memory configurations and area occupation　89
2.5.3　Storage capacities　90
2.5.4　Wiring and the costs of going off-chip　91
2.5.5　Latency and timing　91
2.5.6　Digest　92
2.6　Equivalence transforms for nonrecursive computations　93
2.6.1　Retiming　94
2.6.2　Pipelining revisited　95
2.6.3　Systolic conversion　97
2.6.4　Iterative decomposition and time-sharing revisited　98
2.6.5　Replication revisited　98
2.6.6　Digest　99
2.7　Equivalence transforms for recursive computations　99
2.7.1　The feedback bottleneck　100
2.7.2　Unfolding of first-order loops　101
2.7.3　Higher-order loops　103
2.7.4　Time-variant loops　105
2.7.5　Nonlinear or general loops　106
2.7.6　Pipeline interleaving is not an equivalence transform　109
2.7.7　Digest　111
2.8　Generalizations of the transform approach　112
2.8.1　Generalization to other levels of detail　112
2.8.2　Bit-serial architectures　113
2.8.3　Distributed arithmetic　116
2.8.4　Generalization to other algebraic structures　118
2.8.5　Digest　121
2.9　Conclusions　122
2.9.1　Summary　122
2.9.2　The grand architectural alternatives from an energy point of view　124
2.9.3　A guide to evaluating architectural alternatives　126
2.10　Problems　128
2.11　Appendix I： A brief glossary of algebraic structures　130
2.12　Appendix II： Area and delay figures of VLSI subfunctions　133

Chapter 3　Functional Verification　136
3.1　How to establish valid functional specifications　137
3.1.1　Formal specification　138
3.1.2　Rapid prototyping　138
3.2　Developing an adequate simulation strategy　139
3.2.1　What does it take to uncover a design flaw during simulation?　139
3.2.2　Stimulation and response checking must occur automatically　140
3.2.3　Exhaustive verification remains an elusive goal　142
3.2.4　All partial verification techniques have their pitfalls　143
3.2.5　Collecting test cases from multiple sources helps　150
3.2.6　Assertion-based verification helps　150
3.2.7　Separating test development from circuit design helps　151
3.2.8　Virtual prototypes help to generate expected responses　153
3.3　Reusing the same functional gauge throughout the entire design cycle　153
3.3.1　Alternative ways to handle stimuli and expected responses　155
3.3.2　Modular testbench design　156
3.3.3　A well-defined schedule for stimuli and responses　156
3.3.4　Trimming run times by skipping redundant simulation sequences　159
3.3.5　Abstracting to higher-level transactions on higher-level data　160
3.3.6　Absorbing latency variations across multiple circuit models　164
3.4　Conclusions　166
3.5　Problems　168
3.6　Appendix I： Formal approaches to functional verification　170
3.7　Appendix II： Deriving a coherent schedule for simulation and test　171

Chapter 4　Modelling Hardware with VHDL　175
4.1　Motivation　175
4.1.1　Why hardware synthesis?　175
4.1.2　What are the alternatives to VHDL?　176
4.1.3　What are the origins and aspirations of the IEEE 1076 standard?　176
4.1.4　Why bother learning hardware description languages?　179
4.1.5　Agenda　180
4.2　Key concepts and constructs of VHDL　180
4.2.1　Circuit hierarchy and connectivity　181
4.2.2　Concurrent processes and process interaction　185
4.2.3　A discrete replacement for electrical signals　192
4.2.4　An event-based concept of time for governing simulation　200
4.2.5　Facilities for model parametrization　211
4.2.6　Concepts borrowed from programming languages　216
4.3　Putting VHDL to service for hardware synthesis　223
4.3.1　Synthesis overview　223
4.3.2　Data types　224
4.3.3　Registers， finite state machines， and other sequential subcircuits　225
4.3.4　RAMs， ROMs， and other macrocells　231
4.3.5　Circuits that must be controlled at the netlist level　233
4.3.6　Timing constraints　234
4.3.7　Limitations and caveats for synthesis　238
4.3.8　How to establish a register transfer-level model step by step　238
4.4　Putting VHDL to service for hardware simulation　242
4.4.1　Ingredients of digital simulation　242
4.4.2　Anatomy of a generic testbench　242
4.4.3　Adapting to a design problem at hand　245
4.4.4　The VITAL modelling standard IEEE 1076.4　245
4.5　Conclusions　247
4.6　Problems　248
4.7　Appendix I： Books and Web Pages on VHDL　250
4.8　Appendix II： Related extensions and standards　251
4.8.1　Protected shared variables IEEE 1076a　251
4.8.2　The analog and mixed-signal extension IEEE 1076.1　252
4.8.3　Mathematical packages for real and complex numbers IEEE 1076.2　253
4.8.4　The arithmetic packages IEEE 1076.3　254
4.8.5　A language subset earmarked for synthesis IEEE 1076.6　254
4.8.6　The standard delay format (SDF) IEEE 1497　254
4.8.7　A handy compilation of type conversion functions　255
4.9　Appendix III： Examples of VHDL models　256
4.9.1　Combinational circuit models　256
4.9.2　Mealy， Moore， and Medvedev machines　261
4.9.3　State reduction and state encoding　268
4.9.4　Simulation testbenches　270
4.9.5　Working with VHDL tools from different vendors　285

Chapter 5　The Case for Synchronous Design　286
5.1　Introduction　286
5.2　The grand alternatives for regulating state changes　287
5.2.1　Synchronous clocking　287
5.2.2　Asynchronous clocking　288
5.2.3　Self-timed clocking　288
5.3　Why a rigorous approach to clocking is essential in VLSI　290
5.3.1　The perils of hazards　290
5.3.2　The pros and cons of synchronous clocking　291
5.3.3　Clock-as-clock-can is not an option in VLSI　293
5.3.4　Fully self-timed clocking is not normally an option either　294
5.3.5　Hybrid approaches to system clocking　294
5.4　The dos and don’ts of synchronous circuit design　296
5.4.1　First guiding principle： Dissociate signal classes!　296
5.4.2　Second guiding principle： Allow circuits to settle before clocking!　298
5.4.3　Synchronous design rules at a more detailed level　298
5.5　Conclusions　306
5.6　Problems　306
5.7　Appendix： On identifying signals　307
5.7.1　Signal class　307
5.7.2　Active level　308
5.7.3　Signaling waveforms　309
5.7.4　Three-state capability 311
5.7.5　Inputs， outputs， and bidirectional terminals　311
5.7.6　Present state vs. next state　312
5.7.7　Syntactical conventions　312
5.7.8　A note on upper- and lower-case letters in VHDL　313
5.7.9　A note on the portability of names across EDA platforms　314

Chapter 6　Clocking of Synchronous Circuits　315
6.1　What is the difficulty in clock distribution?　315
6.1.1　Agenda　316
6.1.2　Timing quantities related to clock distribution　317
6.2　How much skew and jitter does a circuit tolerate?　317
6.2.1　Basics 317
6.2.2　Single-edge-triggered one-phase clocking　319
6.2.3　Dual-edge-triggered one-phase clocking　326
6.2.4　Symmetric level-sensitive two-phase clocking　327
6.2.5　Unsymmetric level-sensitive two-phase clocking　331
6.2.6　Single-wire level-sensitive two-phase clocking　334
6.2.7　Level-sensitive one-phase clocking and wave pipelining　336
6.3　How to keep clock skew within tight bounds　339
6.3.1　Clock waveforms　339
6.3.2　Collective clock buffers　340
6.3.3　Distributed clock buffer trees　343
6.3.4　Hybrid clock distribution networks　344
6.3.5　Clock skew analysis　345
6.4　How to achieve friendly input/output timing　346
6.4.1　Friendly as opposed to unfriendly I/O timing　346
6.4.2　Impact of clock distribution delay on I/O timing　347
6.4.3　Impact of PTV variations on I/O timing　349
6.4.4　Registered inputs and outputs　350
6.4.5　Adding artificial contamination delay to data inputs　350
6.4.6　Driving input registers from an early clock　351
6.4.7　Tapping a domain’s clock from the slowest component therein　351
6.4.8　“Zero-delay” clock distribution by way of a DLL or PLL　352
6.5　How to implement clock gating properly　353
6.5.1　Traditional feedback-type registers with enable　353
6.5.2　A crude and unsafe approach to clock gating　354
6.5.3　A simple clock gating scheme that may work under certain conditions　355
6.5.4　Safe clock gating schemes　355
6.6　Summary　357
6.7　Problems　361

Chapter 7　Acquisition of Asynchronous Data　364
7.1　Motivation　364
7.2　The data consistency problem of vectored acquisition　366
7.2.1　Plain bit-parallel synchronization　366
7.2.2　Unit-distance coding　367
7.2.3　Suppression of crossover patterns　368
7.2.4　Handshaking　369
7.2.5　Partial handshaking　371
7.3　The data consistency problem of scalar acquisition　373
7.3.1　No synchronization whatsoever　373
7.3.2　Synchronization at multiple places　373
7.3.3　Synchronization at a single place　373
7.3.4　Synchronization from a slow clock　374
7.4　Metastable synchronizer behavior　374
7.4.1　Marginal triggering and how it becomes manifest　374
7.4.2　Repercussions on circuit functioning　378
7.4.3　A statistical model for estimating synchronizer reliability　379
7.4.4　Plesiochronous interfaces　381
7.4.5　Containment of metastable behavior　381
7.5　Summary　384
7.6　Problems　384

Chapter 8　Gate- and Transistor-Level Design　386
8.1　CMOS logic gates　386
8.1.1　The MOSFET as a switch　387
8.1.2　The inverter　388
8.1.3　Simple CMOS gates　396
8.1.4　Composite or complex gates　399
8.1.5　Gates with high-impedance capabilities　403
8.1.6　Parity gates　406
8.1.7　Adder slices　407
8.2　CMOS bistables　409
8.2.1　Latches　410
8.2.2　Function latches　412
8.2.3　Single-edge-triggered flip-flops　413
8.2.4　The mother of all flip-flops　415
8.2.5　Dual-edge-triggered flip-flops　417
8.2.6　Digest　418
8.3　CMOS on-chip memories　418
8.3.1　Static RAM　418
8.3.2　Dynamic RAM　423
8.3.3　Other differences and commonalities　424
8.4　Electrical CMOS contraptions　425
8.4.1　Snapper　425
8.4.2　Schmitt trigger　426
8.4.3　Tie-off cells　427
8.4.4　Filler cell or fillcap　428
8.4.5　Level shifters and input/output buffers　429
8.4.6　Digitally adjustable delay lines　429
8.5　Pitfalls　430
8.5.1　Busses and three-state nodes　430
8.5.2　Transmission gates and other bidirectional components　434
8.5.3　What do we mean by safe design?　437
8.5.4　Microprocessor interface circuits　438
8.5.5　Mechanical contacts　440
8.5.6　Conclusions　440
8.6　Problems　442
8.7　Appendix I： Summary on electrical MOSFET models　445
8.7.1　Naming and counting conventions　445
8.7.2　The Sah model　446
8.7.3　The Shichman–Hodges model　450
8.7.4　The alpha-power-law model　450
8.7.5　Second-order effects　452
8.7.6　Effects not normally captured by transistor models　455
8.7.7　Conclusions　456
8.8　Appendix II： The Bipolar Junction Transistor　457

Chapter 9　Energy Efficiency and Heat Removal　459
9.1　What does energy get dissipated for in CMOS circuits?　459
9.1.1　Charging and discharging of capacitive loads　460
9.1.2　Crossover currents　465
9.1.3　Resistive loads　467
9.1.4　Leakage currents　468
9.1.5　Total energy dissipation　470
9.1.6　CMOS voltage scaling　471
9.2　How to improve energy efficiency　474
9.2.1　General guidelines　474
9.2.2　How to reduce dynamic dissipation　476
9.2.3　How to counteract leakage　482
9.3　Heat flow and heat removal　488
9.4　Appendix I： Contributions to node capacitance　490
9.5　Appendix II： Unorthodox approaches　491
9.5.1　Subthreshold logic　491
9.5.2　Voltage-swing-reduction techniques　492
9.5.3　Adiabatic logic　492

Chapter 10　Signal Integrity　495
10.1　Introduction　495
10.1.1　How does noise enter electronic circuits?　495
10.1.2　How does noise affect digital circuits?　496
10.1.3　Agenda　499
10.2　Crosstalk　499
10.3　Ground bounce and supply droop　499
10.3.1　Coupling mechanisms due to common series impedances　499
10.3.2　Where do large switching currents originate?　501
10.3.3　How severe is the impact of ground bounce?　501
10.4　How to mitigate ground bounce　504
10.4.1　Reduce effective series impedances　505
10.4.2　Separate polluters from potential victims　510
10.4.3　Avoid excessive switching currents　513
10.4.4　Safeguard noise margins　517
10.5　Conclusions　519
10.6　Problems　519
10.7　Appendix： Derivation of second-order approximation　521

Chapter 11　Physical Design　523
11.1　Agenda　523
11.2　Conducting layers and their characteristics　523
11.2.1　Geometric properties and layout rules　523
11.2.2　Electrical properties　527
11.2.3　Connecting between layers　527
11.2.4　Typical roles of conducting layers　529
11.3　Cell-based back-end design　531
11.3.1　Floorplanning　531
11.3.2　Identify major building blocks and clock domains　532
11.3.3　Establish a pin budget　533
11.3.4　Find a relative arrangement of all major building blocks　534
11.3.5　Plan power， clock， and signal distribution　535
11.3.6　Place and route (P&R;)　538
11.3.7　Chip assembly　539
11.4　Packaging　540
11.4.1　Wafer sorting　543
11.4.2　Wafer testing　543
11.4.3　Backgrinding and singulation　544
11.4.4　Encapsulation　544
11.4.5　Final testing and binning　544
11.4.6　Bonding diagram and bonding rules　545
11.4.7　Advanced packaging techniques　546
11.4.8　Selecting a packaging technique　551
11.5　Layout at the detail level　551
11.5.1　Objectives of manual layout design　552
11.5.2　Layout design is no WYSIWYG business　552
11.5.3　Standard cell layout　556
11.5.4　Sea-of-gates macro layout　559
11.5.5　SRAM cell layout　559
11.5.6　Lithography-friendly layouts help improve fabrication yield　561
11.5.7　The mesh， a highly efficient and popular layout arrangement　562
11.6　Preventing electrical overstress　562
11.6.1　Electromigration　562
11.6.2　Electrostatic discharge　565
11.6.3　Latch-up　571
11.7　Problems　575
11.8　Appendix I： Geometric quantities advertized in VLSI　576
11.9　Appendix II： On coding diffusion areas in layout drawings　577
11.10　Appendix III： Sheet resistance　579

Chapter 12　Design Verification　581
12.1　Uncovering timing problems　581
12.1.1　What does simulation tell us about timing problems?　581
12.1.2　How does timing verification help?　585
12.2　How accurate are timing data?　587
12.2.1　Cell delays　588
12.2.2　Interconnect delays and layout parasitics　593
12.2.3　Making realistic assumptions is the point　597
12.3　More static verification techniques　598
12.3.1　Electrical rule check　598
12.3.2　Code inspection　599
12.4　Post-layout design verification　601
12.4.1　Design rule check　602
12.4.2　Manufacturability analysis　604
12.4.3　Layout extraction　605
12.4.4　Layout versus schematic　605
12.4.5　Equivalence checking 606
12.4.6　Post-layout timing verification　606
12.4.7　Power grid analysis　607
12.4.8　Signal integrity analysis　607
12.4.9　Post-layout simulations　607
12.4.10　The overall picture　607
12.5　Conclusions　608
12.6　Problems　609
12.7　Appendix I： Cell and library characterization　611
12.8　Appendix II： Equivalent circuits for interconnect modelling　612

Chapter 13　VLSI Economics and Project Management　615
13.1　Agenda　615
13.2　Models of industrial cooperation　617
13.2.1　Systems assembled from standard parts exclusively　617
13.2.2　Systems built around program-controlled processors　618
13.2.3　Systems designed on the basis of field-programmable logic　619
13.2.4　Systems designed on the basis of semi-custom ASICs　620
13.2.5　Systems designed on the basis of full-custom ASICs　622
13.3　Interfacing within the ASIC industry　623
13.3.1　Handoff points for IC design data　623
13.3.2　Scopes of IC manufacturing services　624
13.4　Virtual components　627
13.4.1　Copyright protection vs. customer information　627
13.4.2　Design reuse demands better quality and more thorough verification　628
13.4.3　Many existing virtual components need to be reworked　629
13.4.4　Virtual components require follow-up services　629
13.4.5　Indemnification provisions　630
13.4.6　Deliverables of a comprehensive VC package　630
13.4.7　Business models　631
13.5　The costs of integrated circuits　632
13.5.1　The impact of circuit size　633
13.5.2　The impact of the fabrication process　636
13.5.3　The impact of volume　638
13.5.4　The impact of configurability　639
13.5.5　Digest　640
13.6　Fabrication avenues for small quantities　642
13.6.1　Multi-project wafers　642
13.6.2　Multi-layer reticles　643
13.6.3　Electron beam lithography　643
13.6.4　Laser programming　643
13.6.5　Hardwired FPGAs and structured ASICs　644
13.6.6　Cost trading　644
13.7　The market side　645
13.7.1　Ingredients of commercial success　645
13.7.2　Commercialization stages and market priorities　646
13.7.3　Service versus product　649
13.7.4　Product grading　650
13.8　Making a choice　651
13.8.1　ASICs yes or no?　651
13.8.2　Which implementation technique should one adopt?　655
13.8.3　What if nothing is known for sure?　657
13.8.4　Can system houses afford to ignore microelectronics?　658
13.9　Keys to successful VLSI design　660
13.9.1　Project definition and marketing　660
13.9.2　Technical management　661
13.9.3　Engineering　662
13.9.4　Verification　665
13.9.5　Myths　665
13.10　Appendix： Doing business in microelectronics　667
13.10.1　Checklists for evaluating business partners and design kits　667
13.10.2　Virtual component providers　669
13.10.3　Selected low-volume providers　669
13.10.4　Cost estimation helps　669

Chapter 14　A Primer on CMOS Technology　671
14.1　The essence of MOS device physics　671
14.1.1　Energy bands and electrical conduction　671
14.1.2　Doping of semiconductor materials　672
14.1.3　Junctions， contacts， and diodes　674
14.1.4　MOSFETs　676
14.2　Basic CMOS fabrication flow　682
14.2.1　Key characteristics of CMOS technology　682
14.2.2　Front-end-of-line fabrication steps　685
14.2.3　Back-end-of-line fabrication steps　688
14.2.4　Process monitoring　689
14.2.5　Photolithography　689
14.3　Variations on the theme　697
14.3.1　Copper has replaced aluminum as interconnect material　697
14.3.2　Low-permittivity interlevel dielectrics are replacing silicon dioxide　698
14.3.3　High-permittivity gate dielectrics to replace silicon dioxide　699
14.3.4　Strained silicon and SiGe technology　701
14.3.5　Metal gates bound to come back　702
14.3.6　Silicon-on-insulator (SOI) technology　703

Chapter 15　Outlook　706
15.1　Evolution paths for CMOS technology　706
15.1.1　Classic device scaling　706
15.1.2　The search for new device topologies　709
15.1.3　Vertical integration　711
15.1.4　The search for better semiconductor materials　712
15.2　Is there life after CMOS?　714
15.2.1　Non-CMOS data storage　715
15.2.2　Non-CMOS data processing　716
15.3　Technology push　719
15.3.1　The so-called industry “laws” and the forces behind them　719
15.3.2　Industrial roadmaps　721
15.4　Market pull　723
15.5　Evolution paths for design methodology　724
15.5.1　The productivity problem　724
15.5.2　Fresh approaches to architecture design　727
15.6　Summary　729
15.7　Six grand challenges　730
15.8　Appendix： Non-semiconductor storage technologies for comparison　731

Appendix A　Elementary Digital Electronics　732
A.1　Introduction　732
A.1.1　Common number representation schemes　732
A.1.2　Notational conventions for two-valued logic　734
A.2　Theoretical background of combinational logic　735
A.2.1　Truth table　735
A.2.2　The n-cube　736
A.2.3　Karnaugh map　736
A.2.4　Program code and other formal languages　736
A.2.5　Logic equations　737
A.2.6　Two-level logic　738
A.2.7　Multilevel logic 740
A.2.8　Symmetric and monotone functions　741
A.2.9　Threshold functions　741
A.2.10　Complete gate sets　742
A.2.11　Multi-output functions　742
A.2.12　Logic minimization　743
A.3　Circuit alternatives for implementing combinational logic　747
A.3.1　Random logic　747
A.3.2　Programmable logic array (PLA)　747
A.3.3　Read-only memory (ROM)　749
A.3.4　Array multiplier　749
A.3.5　Digest　750
A.4　Bistables and other memory circuits　751
A.4.1　Flip-flops or edge-triggered bistables　752
A.4.2　Latches or level-sensitive bistables　755
A.4.3　Unclocked bistables　756
A.4.4　Random access memories (RAMs)　760
A.5　Transient behavior of logic circuits　761
A.5.1　Glitches， a phenomenological perspective　762
A.5.2　Function hazards， a circuit-independent mechanism　763
A.5.3　Logic hazards， a circuit-dependent mechanism　764
A.5.4　Digest　765
A.6　Timing quantities　766
A.6.1　Delay quantities apply to combinational and sequential circuits　766
A.6.2　Timing conditions apply to sequential circuits only　768
A.6.3　Secondary timing quantities　770
A.6.4　Timing constraints address synthesis needs　771
A.7　Microprocessor input/output transfer protocols　771
A.8　Summary　773

Appendix B　Finite State Machines　775
B.1　Abstract automata　775
B.1.1　Mealy machine　776
B.1.2　Moore machine　777
B.1.3　Medvedev machine　778
B.1.4　Relationships between finite state machine models　779
B.1.5　Taxonomy of finite state machines　782
B.1.6　State reduction　783
B.2　Practical aspects and implementation issues　785
B.2.1　Parasitic states and symbols　785
B.2.2　Mealy-， Moore-， Medvedev-type， and combinational output bits　787
B.2.3　Through paths and logic instability　787
B.2.4　Switching hazards　789
B.2.5　Hardware costs　790
B.3　Summary　793

Appendix C　VLSI Designer’s Checklist　794
C.1　Design data sanity　794
C.2　Pre-synthesis design verification　794
C.3　Clocking　795
C.4　Gate-level considerations　796
C.5　Design for test　797
C.6　Electrical considerations　798
C.7　Pre-layout design verification　799
C.8　Physical considerations　800
C.9　Post-layout design verification　800
C.10　Preparation for testing of fabricated prototypes　801
C.11　Thermal considerations　802
C.12　Board-level operation and testing　802
C.13　Documentation　802

Appendix D　Symbols and constants　804
D.1　Mathematical symbols used　804
D.2　Abbreviations　807
D.3　Physical and material constants　808

References　811
Index　832

精彩书摘

　　From Algorithms to Architectures
　　2．1 The goals of architecture design
　　VLSI architecture design is concerned with deciding on the necessary hardware resources for solving problems from data and／or signal processing and with organizing their interplay in such a way as to meet target specifications defined by marketing． The foremost concern is to get the desired functionality right．The second priority is to meet some given performance target j often expressed in terms of data throughput or operation rate．A third objective，of economic nature this timej is to minimize production costs．Assuming a given fabrication process，this implies minimizing circuit size and maximizing fabrication yield SO as to obtain as many functioning parts per processed wafer as possible．
　　Another general concern in VLSI design is energy efficiency．Battery-operated equipment，such as hand-held cellular phones，laptop computers，digital hearing aids； etc．，obviously imposes stringent limits on the acceptable power consumption．It is perhaps less evident that energy efficiency is also of interest when power gets supplied from the mains．The reason for this is the cost of removing the heat generated by high．performance high-density ICs．While the VLSI designer is challenged to meet a given performance figure at minimum power in the former case，maximizing performance within a limited power budget is what is sought in the latter．
　　The ability to change from one mode of operation to another in very little time，and the flexibility to accommodate evolving needs and／or to upgrade to future standards are other highly desirable qualities and subsumed here under the term agility．Last but not least，two distinct architectures are likely to differ in terms of the overall engineering effort required to work them out in full detail and，hence also，in their respective times to market．

前言/序言

　　Why this book?
　　Designing integrated electronics has become a multisciplinary enterprise that involves solving problems from fields as disparate as
　　·Hardware architecture
　　·Software engineering
　　·Marketing and investment
　　·Solid-state physics
　　·Systems engineering
　　·Circuit design
　　·Discrete mathematics
　　·Electronic design automation
　　·Layout design
　　·Hardware test equipment and measurement techniques
　　Covering all these subjects is clearly beyond the scope of this text and also beyond the authors proficiency．Yet，I have made an attempt to collect material from the above fields that I have found to be relevant for deciding whether or not to develop digital Very Large Scale Integration(VLSI) circuits，for making major design decisions，and for carrying out the actual engineering work． The present volume has been written with two audiences in mind．As a textbook．it wants to intro- duce engineering students to the beauty and the challenges of digital VLSI design while preventing them from repeating mistakes that others have made before．Practising electronics engineers should find it appealing as a reference book because of its comprehensiveness and the many tables，check- lists，diagrams，and case studies intended to help them not to overlook important action items and alternative options when planning to develop their own hardware components．
　　What sets this book apart from others in the field is its top-down approach．Beginning with hardware architectures，rather than with solid。state physics，naturally follows the normal VLSI design flow and makes the material more accessible to readers with a background in systems engineering， information technology，digital signal processing，or management．

数字集成电路设计：探索微电子世界的奥秘 在当今这个由信息技术驱动的时代，集成电路（Integrated Circuit, IC）无疑是所有电子设备的核心。从智能手机、高性能电脑到尖端的医疗设备和航天科技，无处不见IC的身影。它们是微小世界里的精密巨人，承载着运算、存储、通信等关键功能，是现代文明不可或缺的基石。要深入理解这些“芯片”是如何被设计、制造并最终融入我们生活的方方面面，一本详实而专业的书籍是必不可少的向导。 本书旨在为读者提供一个全面而深入的视角，去探索数字集成电路设计的奇妙世界。我们将从宏观的系统架构出发，层层剖析，直至微观的晶体管层面，揭示从一个抽象的设计理念如何一步步转化为一颗颗闪耀着智慧光芒的芯片。这不是一本简单介绍芯片外观的书籍，而是一次对“芯”世界内在逻辑与工艺的深度挖掘。 一、 架构的蓝图：从宏观到微观的系统构思 任何复杂的系统，都始于一个清晰的架构。在数字集成电路设计领域，这同样适用。我们将首先探讨VLSI（超大规模集成电路）架构的原理与设计方法。VLSI是当今集成电路设计的基石，它意味着将数以亿计的晶体管集成在指甲盖大小的芯片上。这不仅是数量的堆叠，更是对设计效率、性能、功耗和面积的极致追求。 我们会深入研究模块化设计的思想，理解如何将庞大的设计分解为可管理、可复用的子模块。从CPU的指令集架构（ISA）到内存控制器、I/O接口，再到更具体的算术逻辑单元（ALU）、寄存器文件等，我们将逐一剖析这些核心功能单元的设计哲学和实现方式。这部分内容将帮助读者建立起对复杂数字系统高屋建瓴的认识，理解不同模块之间的协同工作原理，以及如何在设计早期就为性能、功耗和可测试性打下坚实基础。 随后，我们将聚焦于逻辑设计。这是从架构描述转化为具体电路实现的桥梁。我们将探讨数字逻辑的基本概念，如布尔代数、逻辑门、组合逻辑和时序逻辑。在此基础上，我们将深入研究可综合硬件描述语言（HDL），例如Verilog或VHDL。这些语言是现代IC设计的标准语言，它们允许工程师用文本的方式来描述硬件的行为和结构。我们将学习如何使用HDL来建模数字电路，如何编写高效且易于理解的代码，以及如何利用HDL进行功能仿真，验证设计的正确性。 更重要的是，我们会探讨逻辑综合的原理。逻辑综合是将HDL代码转化为一系列标准逻辑门（如AND, OR, NOT, XOR等）和触发器（Flip-flops）的优化过程。这个过程需要考虑电路的面积、速度和功耗等多个目标，是一个复杂的优化问题。我们将了解综合工具的工作流程，以及如何通过调整HDL代码和综合选项来影响最终的电路性能。 二、 逻辑的实现：从抽象到物理的电路映射 当逻辑设计完成并经过仿真验证后，下一步是将这些抽象的逻辑门转化为可以在物理芯片上实现的具体电路。这一阶段涉及电路设计，主要关注如何用晶体管构建出逻辑门，以及如何将这些逻辑门连接起来形成功能单元。 我们将详细介绍CMOS（互补金属氧化物半导体）技术，这是当前绝大多数数字集成电路采用的制造工艺。CMOS技术的两大优势——低静态功耗和高集成度——使其成为微电子产业的王者。我们会深入理解CMOS反相器（Inverter）的工作原理，以及如何利用PMOS和NMOS晶体管组合出与门（AND Gate）、或门（OR Gate）等基本逻辑门。 在此基础上，我们将探讨标准单元库（Standard Cell Library）的概念。标准单元库是IC设计中不可或缺的资源，它包含了一系列预先设计好的、经过性能优化和验证的逻辑门和更复杂的逻辑功能单元（如加法器、多路选择器等）。设计人员通过选择和组合这些标准单元，可以快速高效地构建出复杂的数字电路。我们将了解标准单元的设计原则，以及它们在布局布线过程中的作用。 三、 物理的形态：从电路到硅片的转化之旅 将逻辑电路转化为物理实现，是一项极具挑战性的工作，它直接关系到最终芯片的性能、功耗和可靠性。这一阶段涉及到物理设计，包括布局（Placement）和布线（Routing）。 布局是指将标准单元放置在芯片的指定区域内，并确定它们的精确位置。一个好的布局能够最大限度地减少信号延迟，减小线网长度，从而降低功耗和提高性能。我们将学习不同的布局策略，如全局布局、详细布局，以及如何利用工具来优化单元的摆放。 布线则是将这些已布局的单元通过金属导线连接起来，形成完整的电路。导线在芯片上占据宝贵的面积，并且它们本身也存在电阻和电容，会引入延迟和功耗。布线过程需要考虑多层金属的利用，确保信号的连通性，同时又要避免信号冲突和短路。我们将了解各种布线算法和技术，以及如何优化布线以达到性能目标。 此外，我们还将触及时序分析（Timing Analysis）。在高速运行的数字电路中，信号到达的时间至关重要。时序分析用于检查电路是否存在时序违例，例如建立时间（Setup Time）和保持时间（Hold Time）的违例。我们将学习如何使用静态时序分析（STA）工具来评估电路的时序特性，并了解如何通过调整逻辑设计、布局布线来修复时序问题。 四、 制造的艺术：从硅片到成品的功能实现 即便设计得再完美，最终的集成电路也需要通过精密的制造工艺才能在物理世界中实现。这一部分将带领读者一窥CMOS制造的奥秘。 我们将概述光刻（Photolithography）、刻蚀（Etching）、掺杂（Doping）、薄膜沉积（Thin Film Deposition）等一系列关键的制造步骤。我们将了解如何通过光刻技术，将设计好的电路图案精确地转移到硅片上，如何通过刻蚀去除不需要的材料，以及如何通过掺杂来改变半导体的导电特性，从而形成晶体管的源极、漏极和沟道。 我们将深入理解掩模（Mask）的作用，它是制造过程中至关重要的“蓝图”，每一个掩模都对应着芯片制造过程中的一个特定步骤。我们将看到，从一块纯净的硅晶圆，到最终切分成一颗颗功能齐全的芯片，需要经过数百甚至上千道精密的工序。 最后，我们将讨论芯片封装（Packaging）和测试（Testing）。封装是将制造完成的裸片（Die）保护起来，并为其提供与外部电路连接的引脚。测试则是确保每一颗制造出来的芯片都能够按照设计规格正常工作，从而保证产品的质量。 结语 数字集成电路设计是一个融合了计算机科学、电子工程、材料科学和物理学等多个学科的交叉领域。它要求设计者不仅要有扎实的理论基础，还要有丰富的实践经验和解决复杂问题的能力。本书将力求以清晰的逻辑、详实的论述和丰富的示例，带领读者一步步走进这个充满挑战与机遇的微电子世界。通过对VLSI架构、逻辑设计、CMOS电路实现以及制造工艺的全面解读，相信读者能够对数字集成电路的设计过程有一个深刻而系统的理解，为将来在这一领域的发展奠定坚实的基础。

评分☆☆☆☆☆

这是一本我愿意反复翻阅的经典之作。它的价值远不止于技术的传授，更在于它所传达的那种工程精神和科学严谨性。作者对于VLSI体系结构的剖析，精准而深刻，让我能够窥探到现代数字系统设计的核心思想。无论是对流水线、超标量、多核等处理技术原理的阐述，还是对存储器层次结构、总线协议等系统级组件的讲解，都充满了智慧的光芒。每一次阅读，都能发现新的理解。更令人惊喜的是，本书并没有停留在理论层面，而是将目光投向了CMOS制造的实际工艺。作者将那些在洁净室中进行的、纳米级别的精密操作，描绘得清晰可见，让我对芯片的诞生过程有了切实的感受。从晶圆的制备，到光刻、蚀刻、扩散等一系列复杂工序，再到最终的封装测试，每一个环节都体现了人类科技的极致。这本书让我深刻体会到，每一个闪耀在科技前沿的电子设备，都离不开背后庞大而精密的工程体系。

评分☆☆☆☆☆

翻开这本书，仿佛打开了一扇通往微观宇宙的大门，让我得以窥探那些塑造我们数字生活的基石。作者以一种旁征博引、深入浅出的方式，将复杂的VLSI设计理念娓娓道来，让我对集成电路的整个生命周期都有了全新的认知。从最初的系统级架构设计，到具体的逻辑功能实现，再到最终的物理层面的CMOS制造工艺，每一个环节都被剖析得淋漓尽致。我尤其被书中对不同VLSI架构的比较分析所吸引，作者深入浅出地解释了各种架构的优劣势，以及在不同应用场景下的选择依据，这对于我理解现代处理器设计的发展脉络非常有帮助。而关于CMOS制造工艺的部分，虽然涉及大量专业知识，但作者却能用通俗易懂的语言，将那些微观世界的奇妙景象呈现在我眼前，例如光刻、蚀刻、掺杂等工艺过程，不再是冰冷的术语，而是变成了生动的画面。这本书不仅仅是一本技术手册，更像是一部关于创新与工程的史诗，它激发了我对这个领域的无限好奇心，让我渴望进一步探索其深奥的魅力。

评分☆☆☆☆☆

坦白说，我抱着极大的期望来阅读这本书，而它也确实没有辜负我的期待。这本书最让我印象深刻的是它对于“从概念到现实”这一过程的完整呈现。它不像市面上许多教材那样，只专注于某一个特定的技术点，而是将VLSI设计与CMOS制造这两个看似独立的领域，完美地融合在一起，形成了一个有机的整体。作者在讲解VLSI体系结构时，逻辑严谨，层次分明，让我能够清晰地理解从高层设计到底层实现的过程。无论是处理器架构的设计原则，还是数字信号处理的算法实现，书中的论述都深入浅出，极具启发性。而当进入CMOS制造的部分，我更是被作者的专业度和生动性所折服。那些复杂的工艺流程，在作者的笔下变得易于理解，让我看到了半导体工业背后令人惊叹的精密与高效。这本书不仅仅是传授知识，更重要的是它教会了我如何去思考，如何去解决问题，如何去欣赏工程师们在每一个细节上付出的努力。

评分☆☆☆☆☆

阅读此书的体验，简直像是在一次穿越时空的旅行，从抽象的设计概念，一步步走向具象的物理实体。这本书的结构设计非常巧妙，它并没有一开始就钻入晦涩的细节，而是从宏观的VLSI体系结构入手，为读者勾勒出集成电路设计的整体框架。这种由大到小的叙事方式，让我能够更好地理解各个组成部分之间的相互关系，以及它们如何协同工作以实现复杂的功能。当我沉浸在书中对各种处理器架构、内存系统以及通信接口的讨论中时，我仿佛能看到那些工程师们是如何将无数的逻辑门巧妙地组合在一起，构建出强大的计算引擎。随后，当话题转向CMOS制造时，我的震撼更是无以复加。作者将那些纳米级别的精细工艺，如光刻、薄膜沉积、离子注入等，描述得如同发生在眼前一般。我从中体会到了人类智慧的极致，以及工程技术所能达到的高度。这本书让我深刻认识到，一枚小小的芯片，承载的是无数工程师的心血与汗水，是科技进步的结晶。

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一本真正让我醍醐灌顶的工具书，虽然我并非科班出身，但在接触了这本书之后，我对电子世界的奥秘有了前所未有的清晰认识。它就像一位循循善诱的导师，将那些原本遥不可及的概念，比如VLSI的宏伟蓝图，以及CMOS制造背后精密的工艺流程，一点一点地拆解，以一种近乎艺术的方式呈现在我面前。作者的叙述逻辑严谨，从宏观的系统设计理念，深入到微观的晶体管级别，每一个环节的衔接都流畅自然，仿佛在我脑海中构建起一座立体的数字电路模型。我尤其欣赏书中对设计流程的细致描述，从概念的萌芽，到架构的选取，再到逻辑的实现，最后到物理的布局布线，每一个步骤都充满了挑战与智慧。即使是那些涉及物理化学的制造过程，作者也用生动形象的比喻，让我这个非专业人士也能窥见其精妙之处，理解为何一个小小的芯片背后蕴藏着如此庞大的工程。这本书让我意识到，数字集成电路设计绝不仅仅是枯燥的理论堆砌，而是一门融合了科学、工程与艺术的学科，它需要深厚的理论基础，也需要丰富的实践经验。我迫不及待地想将书中的知识应用到我的实际项目中，去创造属于自己的数字世界。

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公司的师傅看了 说是很不错

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做工程的,当工具书印证一下

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英文版

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英文版

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正版， 书不错， 就是边角有点磨了， 快递服务态度也不错

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加油

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公司的师傅看了 说是很不错

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经典中的经典，收藏！

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加油